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? january 2001 1/23 AN1317 - application note non isolated power supplies in buck and inverter configuration using viper20 device a. bailly - s. luciano introduction the viper20 is a full integrated switching device. it replaces the conventional pwm driver circuit, its associated high voltage power mosfet switch and a full set of other passive components, and provide a high level of performance thanks to its current mode structure and standby operation capability. 1. scope the viper20 is initially designed to be used at the primary side of any off line power supplies in isolated flyback configuration but it is also the right solution for different types of not isolated power supplies applications where low power (1w to 5w), wide input voltage range and low prices are required. in this case, a simple two pins inductor can replace an expensive safety transformer. the basic principle of this type of supplies is to convert a high voltage source to a low voltage one by the only way of the switching frequency and duty cycle management. the applications like home appliances (microwave oven, washing machine, triac drivers...), industrial applications (motors control,...) do not require galvanic isolation between the mains lines and the low voltage load, especially when one of the low voltage outputs must be connected to one of the mains lines. all these applications will take benefits from viper20 features: ? full integrated pwm start up current source and high voltage power mosfet, allow to build simple, robust, cost effective and compact power supplies. ? built in overtemperature and overcurrent protection provide a safe control in overload conditions. this application note gives all the elements to enable the designer to start the development of his own non isolated power supply using the viper20. it defines the key components, and highlights the differences between the buck and the inverter (also called buck-boost) topologies. 2. not isolated topologies 2.1 viper20 in buck topology the basic schematic of a viper20 in buck topology delivering 2w typical, with a fixed output voltage, is given fig. 1. the buck structure is composed here by the on chip power mosfet, the inductor l1, the free wheeling diode d3, the output filtering capacitor c5 and the output load itself. in this topology, the viper20 switching duty cycle is very low (a few percent) because of the very high difference between the input and the output voltages. its value would be at the maximum equal to the voltages ratio, when in continuous mode and even less in discontinuous mode. if the switching frequency is too high, the power mosfet conduction time will decrease accordingly, which may result in early burst mode operation if lower than the minimum turn on time of the device. in practice, the chosen
2/23 AN1317 - application note switching frequency will be comprised between 20 khz and 30 khz, just above audible values. during the start up phase, the viper20 is in standby mode and its on chip high voltage current source sources a current on the v dd pin until the voltage across the capacitor c2 reaches the v ddon threshold. then, this current source is turned off and the device starts switching. after a transition phase during which the output voltage grows up, the v dd supply of the viper20 is provided by the capacitor c2 and finally, from the positive output through the diode d2 when the output voltage becomes higher than the current v dd value. figure 1: 2w typical single output not isolated power supply with buck topology in normal operation, the output voltage regulation is achieved by the viper20 error amplifier which accurately compares the v dd value to the internal 13v voltage reference. the forward voltage across the diode d2 is here partially compensated by the forward voltage across the diode d3. so, the output voltage and the on chip voltage reference values are equal, except for diode forward voltage differences due to different diodes current: it is generally higher in the free wheeling diode d3, resulting in a slightly lower output voltage. a typical characteristic of the buck is that the inductor charge and discharge paths are exclusively done through the output load. it is a slight advantage in normal operation because the energy is transferred to the load during both turn on and turn off cycles, but in very low or no load conditions, it has two drawbacks: ? the charge of the start up tank capacitor c2 is impossible, especially when the input voltage is slowly 13v osc comp source drain vdd - + viper20 r2 3.9k c4 100nf r1 10k c3 10nf d1 1n4007 c2 22uf 400v l1 470uh d3 byt01-400v c5 33uf 16v d2 byt01-400v c1 10uf 16v dz1 bzx55c15v ac in ac in +13v gnd out
3/23 AN1317 - application note increased. if no protection is foreseen, it is possible to apply the input voltage directly on the output, with large overvoltages. ? once started, overvoltages may also occur at the output, mainly for low input voltage values. the root cause of the last phenomenon resides in the duty cycle increase at low input voltage, together with a low output load. fig. 2 shows the drain current shape for two input voltages. the lower is the input voltage, and the higher is the turn on. as a consequence, the turn off phase during which the energy is sent to c2 through d2 is reduced, and the device is increasing its drain current to maintain a correct regulated voltage on the v dd pin at 13 v. if the load is not able to absorb the corresponding current during the on phase, overvoltage is resulting on the output. figure 2: drain current for two input voltages in low load conditions fig. 3 shows an extreme case where the phenomenon reaches its critical phase, with a continuous mode of operation. the following computation demonstrates the risk of overvoltage and/or overcurrent on the output. vin = 200v iout = 5ma vin = 50v iout = 5ma 50ma/div - 10s/div
4/23 AN1317 - application note figure 3: switching cycle in continuous mode in low input voltage condition the average currents consumed by the viper20 i dd and the output current i out can be expressed as: and by using these two equations: finally, by introducing the duty cycle expression in continuous mode: the minimum output current mandatory to keep the output voltage under control is given by: to prevent these disturbances resulting in possible output overvoltage or incorrect start up, a 15v zener diode dz1 is added. it allows a current to flow at the output, insuring a correct start up and clamps any possible overvoltage. nevertheless, as shown in the above last formula, the current flowing in this zener can be very high when the input voltage approaches the output one. section 5 describes a schematic modification to overcome this issue. fig. 4 presents the operation of the free wheeling diode in this condition: actually it is always blocked, as the voltage on the cathode never becomes negative. also on this figure, it can be observed that the voltage drop v d across d3 is about 5v while the output voltage is at 15v. it means that v dd is about 10v i dd 1 2t s ------------ - i p i 0 + () t s t on C () = i out 1 2t s ------------ - i p i 0 + () t on = i out t on i dd t s t on C ------------------ = d t on t s ------ v in v out ---------- - == i out i dd v out v in v out C ------------------------- = i p charge discharge i 0 t on ts - t on t i drain p p t s
5/23 AN1317 - application note because the input voltage is too low to insure a proper operation of the converter, which is about to shut down. figure 4: buck non isolated - viper20 source voltage with v in = 47 v, i out =5 ma. dz1 conducting 2.2 viper20 in inverter topology the inverter schematic is derived from the buck one of fig. 1 by just swapping the inductor l1 and the free wheeling diode d3. the resulting schematic is given fig. 5. there is a major difference with the buck from a functional point of view : when the on chip power mosfet is turned on, the inductor l1 does not charge anymore through the load but between the mains lines. the output load now gets all its energy during the mosfet off state, through the inductor l1 and the free wheeling diode d3. as a consequence, the zener diode dz1 is no more necessary because of two reasons: ? the charge of the tank capacitor c2, now independent from the load, is always possible. ? both viper20 supply (v dd pin) and output load are receiving energy form the inductor l1 at the same period of time. so, there is no possible difference between the v dd voltage and the output one, which is always under control. compared to the buck, the current flowing through the load is in the opposite direction so that the output voltage becomes now negative. as a consequence, the output capacitor c5 polarity must be swapped and the anode of the diode d2, supplying the viper20, must now be connected to the ground lead gnd out to insure a correct positive supply to the v dd pin. vd
6/23 AN1317 - application note figure 5: 2w typical single output not isolated power supply with inverter topology 3. design methodology the schematic of either fig. 1 or fig. 5 can be separated into six blocks: ? the oscillator network composed by r1 and c3. ? the buck or inverter structure, which is composed by the on chip mosfet, the inductor l1, the free wheeling diode d3 and the output filtering capacitor c5. ? the viper20 supply circuit, composed by d2 and c2. ? the front rectifier and filter. ? the error amplifier compensation network composed by r2 and c4. all these functions will be detailed in the next paragraphs. 3.1 switching frequency and duty cycle sections 1 and 2 showed that the input voltage transformation is entirely managed by the viper20 which controls the switching duty cycle. whatever the topology is, the goal is to look for the widest load regulation range, trying to reach the viper20 minimum turn on time (t onmin = 500 ns typ.) for the lowest output load. for maximum load, although the viper20 is perfectly compatible from the continuous mode, it must be avoided because the power dissipation in the free wheeling diode d3 would be too high and the inductor size and price would increase. for all the above reasons, these topologies are operated at 13v osc comp source drain vdd - + viper20 r2 3.9k c4 100nf r1 10k c3 10nf d1 1n4007 c1 22uf 400v l1 470uh d3 byt01-400v c5 33uf 16v d2 byt01-400v c2 10uf 16v ac in ac in -13v gnd out
7/23 AN1317 - application note low switching frequency and always in discontinuous mode. as an example, to get a 13v output voltage with a 265 vrms input voltage, the maximum duty cycle would be less than 5%. with a switching frequency of 100 khz, the maximum conduction time would always be equal or lower than t onmin , leading to a permanent burst mode operation. in practice the switching frequency is chosen just above the audio ones, in the 20 khz to 30 khz range and the viper20 will work in discontinuous mode with a duty cycle of about 2% to 3% at high line and about 6% to 10% at low line. from the viper20 datasheet, the switching frequency is given here below: on the schematic of fig. 1 and fig. 5, r1=10k w and c3=10nf have been chosen to get a switching frequency near by 20 khz (21.7 khz typical). 3.2 inductor in normal operation, for both topologies, the switching cycle consists of two phases. first, the power mosfet is switched on during t on , d3 is blocked, the inductor connected to the high voltage source stores the energy. second, the power mosfet is switched off during t dis , the inductor restores its energy to the load through d3, and to the v dd pin through d2. as described in section 2, the load is supplied during t on and t dis with the buck topology, and only during t dis with the inverter one. a typical switching cycle is shown on fig. 6. knowing the output power, the switching frequency and the maximum viper20 peak current, l1 can be computed as follow: for the buck: with and d v out v in ---------- - = f s 2.3 r 1 c 3 ----------------- 1 550 r 1 150 C --------------------- C ? ?? = p out 1 2 -- - l 1 i 2 p f s 1 2 -- - i p v out di dd v out C + = dt on f s = t on v in v out C () l 1 i p = p out 1 2 -- - l 1 i 2 p f s 1 v out v in v out C ------------------------- + ? ?? i dd v out C = l 1 2 p out i dd v out + i 2 p f s 1 v out v in v out C ------------------------- + ? ?? -------------------------------------------------------------- =
8/23 AN1317 - application note figure 6: switching diagram in normal operation (discontinuous mode) for the inverter: in practice, with a less than 10% error, the viper20 consumption and also the power transferred to the load during the conduction time of the mosfet for the buck (v in ?v out ) can be neglected. in this case, the calculation becomes the same for both topologies: for a 2w maximum output power, with i p =i dpeak =0.5a min, f s =20khz, it gives l 1 l 800h. the power delivered by these topologies is limited by the minimum viper20 current capability and by the fact that continuous mode has to be avoided. the maximum output current is therefore about . it gives also a maximum inductance value, for a given frequency: on fig. 9 and 11 of section 4, a 2 w typical output power can be obtained with an inductor value of 470 h (i dlim =0.67a typical). p out 1 2 -- - l 1 i 2 p f s i dd v out C = l 1 2 p out i dd v out + i 2 p f s ----------------------------------------- = l 1 2 p out i 2 p f s ---------------- - ? i dlim 2 --------------- l 1max v out i dlim f s ---------------------- ? charge discharge i drain t s t dis t on t off i p t
9/23 AN1317 - application note 3.3 output capacitor the output capacitor c5 is an element linked with the desired output ripple amplitude d v out , which depends on the output voltage and on the application to supply. the worst case occurs for the maximum load, when the viper20 delivers its maximum peak current during the longer conduction time. the charge of the capacitor c5 is: with the hypothesis that the viper20 is at the limit of the continuous mode, which is a worst case making easier the calculation of the current in the capacitor: example with d v out =100 mvpp, f s =20 khz, i p =i dpeak =0.5 a min, c 5 l 31 f the maximum peak current flowing through this capacitor is during the charge and during the discharge. to avoid an excessive power dissipation in the capacitor and a high output ripple, the esr of the output capacitor must be low. table 1 gives a picture of the esr impact, with =0.7a typical. table 1: output ripple versus capacitor technology the above example illustrates that the computed capacitor value has to be tuned according to the application needs, the capacitor technology and its associated cost. 3.4 viper20 supply circuit for both topologies, fig. 7 shows the three different mode: ? the start up phase: the on chip high voltage current source is turned on. it sources a current out of the v dd pin in order to charge the tank capacitor c2 until the v ddon threshold is reached. this capacitor then supplies the viper20 during the following phase. capacitor type capacitor value esr at 100khz i r at 100khz output ripple v r = i p ? esr standard electrolytic 33 f / 16v 7 w 90 ma 4.9 v electrolytic solid al 33 f / 16v 700 m w 1460 ma 490 mv electrolytic os-con 33 f / 16v 50 m w 1580 ma 35 mv electrolytic low z 270 f / 16v 120 m w 630 ma 84 mv q 5 it d c 5 d v out () = = i dt 1 2 -- - t s 2 ----- i p 2 ---- ? ?? 1 8 -- - t s i p == c 5 1 8 -- - t s i p d v out ----------------- = i p 2 ---- - i p 2 ---- - C i p
10/23 AN1317 - application note ? a transition phase: it takes place immediately after the previous one. the current source is turned off and the device starts switching. at the very beginning, the output voltage is lower than v dd one, the diode d2 is blocked, the viper20 is still supplied by c2. when the output voltage, increasing cycles after cycles, reaches v ddon , d2 conducts, supplying the viper20 from the output. obviously, the value of c2 must be large enough to maintain the v dd voltage above the v ddoff threshold, before being supplied from the output. if it is not the case, the viper20 will loop into endless start up cycles. ? the normal operation: the v dd pin is fully supplied by the low voltage output and regulated at 13 v. figure 7: viper20 supply phases in buck or inverter topologies the calculation of the v dd tank capacitor c2 can be done as follow: the minimum start up time t ss must be higher than the output capacitor c5 charging time t ch , which is function of the nominal output voltage and the average output current: during the very first start up cycles, c5 is empty, the output voltage is more or less null and the viper20 delivers its maximum peak current i dlim during the power mosfet on state. due to the low output voltage, the inductor l1 discharges very slowly (t dis ?t s ) so that the switching is done in continuous mode. at that time, the average output current is almost equal to i dlim . t ss t ch > c 5 v ddoff i outavg ---------------------------- - = tss v out t v dd v ddon v dd off v ddreg start up phase transition phase normal operation tch
11/23 AN1317 - application note while the output voltage grows up, the discontinuous mode is reached and the average output current becomes the half of the maximum peak current: and the average output current for can be approximate as: at the beginning of the start up phase, the capacitor c2 is charged at v ddon , and it can supply the v dd pin down to v ddoff . so, t ss can be expressed as: , with so: finally: with: v out =13v, i dd0 =16ma, i p =i dlim =0.5a min, v ddhyst =2.4v, c 5 =33f, c 2 >7.6 f. 3.5 front rectifier and filter as single wave rectification is chosen because it allows to have the output ground connected to one of the mains lines, as it is required in most of the non isolated applications. as the involved power is low, the input filtering can be achieved without huge bulk capacitor. any usual rectification diode having a reverse voltage of 800 v will fit the needs. on the schematic of fig. 1 and 5, we used the part number 1n4007. the energy stored in the bulk capacitor during the conduction time of the diode must be equal to the total power dissipated when the diode is blocked. referring to fig. 8 and with the efficiency of the converter , it comes: the designer can easily choose v inlow according to the input voltage range and the output ripple he can accept, knowing that a v inlow reasonable value is 70% of v inpeak . t0i outavg i dlim ? t = tt ss i outavg 1 2 -- - i dlim ? t = 0tt ss i outavg 3 4 -- - i dlim ? t ss i ddo c 2 v ddhyst ---------------------- - = v ddhyst v ddon v ddoff C = c 2 i dd0 t ss v ddhyst --------------------- - i dd0 c 5 v out () 3 4 -- - i dlim () v ddhyst ------------------------------------------------------- > = c 2 i dd0 4c 5 v out 3i dlim v ddhyst --------------------------------------------- > h p out p in --------- - = 1 2 -- - c 1 v 2 inpeak v 2 inlow C () t 2 t 1 C () p out 1 h --- =
12/23 AN1317 - application note t 2 and c 1 can now be extracted as follow: , with a wide range input voltage design, fitting both american and european standards, is considered: the minimum ac voltage is 85 vrms, so v inpeak =120v, 60 hz. the designer needs a 2 w maximum output power and he chooses v inlow =80% of v inpeak . knowing that the typical efficiency h for this type of converter is about 70%, he gets c 1 =19.4f. he will retain 22 f which is the closest higher normalized value, with a voltage of 400 v to cover the whole range. 3.6 compensation network the r2 and c4 network connected on the comp pin of the viper20 insures a correct stability of the converter. note that both buck and inverter topologies are working in discontinuous, and have a very similar dynamic behavior. so, the values indicated on the schematics are convenient for both topologies and in all load conditions. v inlow v inpeak 2 p t 2 t s ----- ? ?? sin t 2 t s 2 p ------ arc v inlow v inpeak ------------------ sin t s + = t = c 1 2 t 2 t 1 C () p out 1 h --- v 2 inpeak v 2 low C () ---------------------------------------------- - = t 1 t s 4 ----- = ts v in l ow v dc v in t t 1 t 2 v in peak figure 8: single wave filtering
13/23 AN1317 - application note 4. measurement results the following graphs show typical results using the schematics of fig. 1 and fig. 5. unless specified, the measurements are done at ambient temperature. 4.1 buck and inverter output characteristics figure 9: typical output characteristic of the buck topology figure 10: buck non isolated - output voltage at low load and low input voltage 0 50 100 150 200 250 300 iout (ma) 7 8 9 10 11 12 13 14 15 16 vout (v) vin = 100v vin = 200v vin = 300v 20 30 40 50 60 70 80 90 vin (v) 6 8 10 12 14 16 vout (v) -100ma -30ma -5ma 0ma
14/23 AN1317 - application note fig. 10 illustrates the buck behavior in low load and low input voltage conditions, as described in section 2.1. the output voltage is clamped to 15v by the zener diode. at the opposite, as shown in fig. 11 and fig. 12, the output voltage regulation of the inverter is much better whatever are the load and the input voltage. figure 11: typical output characteristic of the fig. 5 inverter schematic figure 12: inverter non isolated - output voltage versus load and input voltage 0 50 100 150 200 250 300 -iout (ma) 7 8 9 10 11 12 13 14 -vout (v) vin = 200v vin = 100v vin = 300v 0 50 100 150 200 250 300 350 vin (v) 0 5 10 15 -vout (v) -100ma -30ma -5ma 0ma
15/23 AN1317 - application note 4.2 buck and inverter power measurements figure 13: buck non isolated - input power versus output power figure 14: inverter non isolated - input power versus output power 00.51 1.5 2 2.5 3 pout (w) 0 0.5 1 1.5 2 2.5 3 3.5 4 pin (w) vin = 300v vin = 100v vin = 200v pout(w) vin = 300v vin = 200v vin = 100v 00.511.52 2.5 0 0.5 1 1.5 2 2.5 3 3.5 pin(w )
16/23 AN1317 - application note figure 15: typical efficiency of a buck non isolated figure 16: typical efficiency of an non isolated inverter 4.3 short circuit fig. 17 shows the inductor current when submitted to a short circuit on the output. it can be seen that this current exceeds the current limitation of the viper20 (it is about 3 a for a limitation of 0.67 a for the 050 100 150 200 250 300 iout (ma) 0% 10% 20% 30% 40% 50% 60% 70% 80% efficiency vin = 100v vin = 200v vin = 300 v 0 50 100 150 200 250 300 -iout (ma) 0% 10% 20% 30% 40% 50% 60% 70% 80% efficiency vin = 100v vin = 200v vin = 300v
17/23 AN1317 - application note device). this situation is due to the fact that the minimum turn on of the device is not sufficiently short to keep the drain current under control, especially because the inductor is saturated. figure 17: buck non isolated - inductor current in short circuit condition at v in = 400 v nevertheless, the device is protected against such events and can be connected directly across the front bulk capacitor charged at 400 v without any problem. this corresponds to the worst case of a saturated transformer, which is never reached practically. would it happen, the resulting power dissipation would be limited by the thermal shutdown of the device. figure 18: buck non isolated - short circuit output current at v in = 400 v
18/23 AN1317 - application note fig. 18 represents the output short circuit current. its duty cycle is about 27% for a peak value of 1.4 a. this results in an average current of 0.4 a which is perfectly compatible with the type of diodes generally used for rectifying the output. actually, these types of converter can withstand the short circuit condition indefinitely. the temperature elevation of the components is quite moderate. 5. schematics improvements and variants 5.1 non isolated buck with output overvoltage protection the inherent inconvenient of the buck, already described in paragraph 2.1 and 4.1, is the output voltage increase, in low load and low input voltage conditions. on the initial schematic of fig. 1, the zener diode properly clamps the output voltage surges when a minimum load is guaranteed and if the input voltage rise and fall times between 20v to 50v typical, is short enough. otherwise, the output voltage may rise such values that the power dissipation in dz1 becomes very high, as shown on fig. 19. figure 19: buck non isolated - dz1 power dissipation in short circuit the solution implemented on the schematic of fig. 20, allows to drastically improve the output voltage control, by reducing the nominal switching frequency if the input voltage decreases below a threshold. this frequency shifter consists of a diode d4 connected on the osc pin of the viper20, and receiving a fraction of the input voltage through r3 and r4. when the input voltage becomes low, a current is sunk through d4 from the middle point of the oscillator network r1-c3, thus increasing the charging time of c3 and decreasing the switching frequency. the resistances r3 and r4 are chosen in such a way that the frequency begins to decrease at 100 vdc of input bulk voltage, and stops completely the oscillator at 30 vdc. fig. 21 and 22 illustrates this behavior for two input voltages, and the final results is shown on fig. 23: overvoltages still occur at low input voltage or at low output load conditions, but with a reasonable amount of power dissipated in the clamping zener diode. 20 40 60 80 100 120 vin (v) 0 100 200 300 400 500 600 pz (mw)
19/23 AN1317 - application note figure 20: buck non isolated with switching frequency shifter figure 21: nominal oscillator frequency at v in = 140v 13v osc comp source drain vdd - + viper20 r3 3.9k c4 100nf r2 56k c3 2.2nf d1 1n4007 c2 22uf 400v l1 470uh d3 byt01-400v c5 33uf 16v d2 byt01-400v c1 10uf 16v dz1 bzx55c15v r1 470k r4 33k d4 1n4148 ac in ac in +13v gnd out
20/23 AN1317 - application note figure 22: shifted oscillator frequency at v in =70v figure 23: buck non isolated - output voltage response with frequency shifter 20 30 40 50 60 70 80 90 vin (v) 6 8 10 12 14 16 vout (v) -100ma -30ma -5ma 0ma
21/23 AN1317 - application note 5.2 adjustable output voltage structures on the schematics of fig. 1 and 5, the output voltage is fixed and equal to the reference voltage of the viper20, that is to say 13 v. when different voltages are needed, it is possible to modify these basic structures to get other values. fig. 24 presents a +23v output non isolated buck converter with a zener diode dz2 in series with the v dd pin which imposes the output voltage to be 10 v higher than the reference of the viper20. as a results, the output voltage will be regulated at +23 v. the resistor r1, optionally added here on the line input, is an example of an inrush limiter and filter. when lower output voltages are specified, an another configuration can be used, as shown on fig. 25. an inductor with an intermediate tap is used in order to deliver a -5 v. this inductor can be of the same type than an inexpensive drum vertically mounted on a pcb, except that three pins are provided instead of two for a standard inductor. figure 24: buck non isolated - output voltage increased 13v osc comp source drain vdd - + u1 viper20 r3 3.9k c4 100nf 10k r2 c3 10nf d1 1n4007 c1 22uf 400v l1 470uh d3 byt01-400v c5 33uf 16v d2 byt01-400v c2 10uf 16v dz1 bzx55cxxv c6 2.2uf 35v dz2 bzx55c10v ac in ac in +23v gnd out 100 r1
22/23 AN1317 - application note figure 25: non isolated inverter - reduced output voltage. 6. conclusion it has been demonstrated that the simple topologies as the buck or the inverter can be used directly on off line applications to build efficient non isolated power supplies in the range of a few watts. a viper20 device can minimize the total number of components by offering the error amplifier, the pwm and the power mosfet together inside a single piece of silicon. a special care must be taken when designing the buck topology, as it can provide serious output overvoltages in case of low input voltage, and/or low output load. a simple zener diode on the output, or a more efficient switching frequency shifter network can overcome this issue. the benefits of such low power structures over more conventional 50 hz transformers followed by rectifiers, filters and serial regulators can be listed as follow: ? wide range of input voltages with good output regulation ? higher efficiency and lower standby consumption ? lighter weight, with direct implementation on a standard pcb ac in -xxv gnd out ac in d1 1n4007 c3 10nf d2 byt01-400v d3 byt01-400v c1 1uf 400v 13v osc comp source drain vdd - + u1 viper20 c5 22uf 16v l1 470uh r3 3.9k c2 10uf 16v c4 100nf r2 10k
23/23 AN1317 - application note 1 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy- all rights reserved. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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